Continued innovations in semiconductor process technologies are enabling higher integration densities and device scaling. As semiconductor manufacturing technologies continue to evolve toward smaller design rules and higher integration densities (e.g., 14 nm technology node and beyond), integrated circuit devices and components become increasingly smaller, creating challenges in layout formation and device optimization. Currently, FinFET technologies are typically implemented for FET fabrication, as such technologies provide effective CMOS scaling solutions for FET fabrication at, and below, the 14 nm technology node. A FinFET device comprises a three-dimensional fin-shaped FET structure which includes at least one vertical semiconductor fin structure formed on a substrate, a gate structure formed over a portion of the vertical semiconductor fin, and source/drain regions formed from portions of the vertical semiconductor fin which extend from both sides of the gate structure. The portion of the vertical semiconductor fin that is covered by the gate structure between the source/drain regions comprises a channel region of the FinFET device.
While technological improvements in source/drain contact fabrication techniques have provided a dramatic reduction in the resistance of FET devices, techniques for reducing the parasitic capacitance between active FET devices have become more crucial for improving device performance and reducing power consumption. In general, a reduction in the parasitic capacitance between active devices can be achieved by utilizing a low-k dielectric material to form an initial interlayer dielectric (ILD) layer at the contact/transistor level, which encapsulates the source/drain contacts and metal gate structures. However, the low-k dielectric material that forms the initial ILD layer can become damaged and contaminated as a result of the various fabrication processes (e.g., reactive ion etching, thermal annealing, chemical mechanical polishing, etc.) that are utilized to form source/drain contacts (e.g., trench silicide contacts) and metal gates (e.g., replacement metal gate process), etc., wherein such damage and contamination leads to an undesirable increase in the effective dielectric constant of the initial low-k ILD layer.